MV-1FZ P2 Start Not Working

GadgetUK · Nov 5, 2013

Hi, I've found a fault on my MV-1FZ. The player 2 start button does not work. Using logic probe I've traced from the port, through a few vias and the signal correctly reaches NEO-C1. Does anyone know how it gets from there to an address that the CPU can read (380000h bit 2 apparently). Am I looking at a faulty NEO-C1 here?

shadowkn55 · Nov 5, 2013

It's read through 68k D10. If P1 Left and P2 Left work, I'm inclined to think the fault lies somewhere between C1 and the jamma edge. If you put the multimeter on C1 pin 71, it should read high. When you push the start button, it should read low. If the voltage level doesn't change, it means the problem is the RRC or a broken trace. You can try grounding pin 71 and see if that elicits any action.

GadgetUK · Nov 5, 2013

shadowkn55 said:
It's read through 68k D10. If P1 Left and P2 Left work, I'm inclined to think the fault lies somewhere between C1 and the jamma edge. If you put the multimeter on C1 pin 71, it should read high. When you push the start button, it should read low. If the voltage level doesn't change, it means the problem is the RRC or a broken trace. You can try grounding pin 71 and see if that elicits any action.

Thanks ever so much - it's hard to read the schematics! I've already proven the traces are OK - I can see it change from high to low when P2 start is pressed at entry to C1 chip. I've also forced a low on that pin and it doesn't register in test mode. I am praying that there's a broken trace between C1 and CPU, assuming that's how it works? Worst case I am trying to think how I could design a solution around this, perhaps using an AND gate somehow so when CPU reads from C1 I could push the select signal through a NOT gate directly to D10, but this assumes that the input is read in parallel and not serial or something. Can't check now but will look at D10 tomorrow.

Thanks!!

GadgetUK · Nov 5, 2013

I meant push the 'start signal' not 'select' btw. It's the start button.

GadgetUK · Nov 5, 2013

Does it pass through a 74LS245?

shadowkn55 · Nov 5, 2013

The three sets of joystick inputs are all sent to the 68k through the same data bus, d15-d8. What comes out of c1 depends on the address the 68k is requesting. You need to confirm whether or not the other two joystick inputs are registering or not. Those are output along the same data pins as your non-working start button. If those work, your c1 is busted.

GadgetUK · Nov 5, 2013

shadowkn55 said:
The three sets of joystick inputs are all sent to the 68k through the same data bus, d15-d8. What comes out of c1 depends on the address the 68k is requesting. You need to confirm whether or not the other two joystick inputs are registering or not. Those are output along the same data pins as your non-working start button. If those work, your c1 is busted.

Yes, all other input work OK - looks like its the C1 then =( need to find a way to work out how to hack a fix onto this then...

Thanks

GadgetUK · Nov 5, 2013

OK, here's my proposed solution:-

If I use a couple of AND chips, and presumably a NOT gate to inverse the button output, and use the following logic.

Condition = correct address lines high (380000h), and some yet to identify pin from CPU or C1 to identify CPU is requesting read from C1, then I can AND output of inverted button directly to D10? Does that sound like it would work?

The only issue as far as I can see is I need to identify what pin on CPU changes state to indicate its going to read? Infact, maybe the address is all I need to feed into the AND gates?

Xian Xi · Nov 5, 2013

Just to confirm, you made sure the resistor array/networks are good?

JAMMA edge-->Resistor array input-->Resistor array output-->Neo-C1

GadgetUK · Nov 6, 2013

Xian Xi said:
Just to confirm, you made sure the resistor array/networks are good?

JAMMA edge-->Resistor array input-->Resistor array output-->Neo-C1

Yes, sadly I think it's the C1. I can see the logic level go from high to low when pressing P2 start at the output of resistor network, at the 2 or 3 vias, and on the pin of C1. I've also shorted accidentally to the pin next to it and can see that the start button signal can cause select to be pressed - ie when temporarily shorting start pin on C1 to select pin on C1 - select registers a press, start does not.

Looking at the developers guide I can now see that the 3 addresses for 3 lots of control inputs each use bit 2 (D10) for P2 start, P2 left, and P1 left, so unless there are separate outputs to D10 for each of the addresses then It must be C1 =\

Anyone know where I might buy a spare C1? I am tempted to use 2 or 3 AND gates as proposed above, in order to feed the inverted input into D10 when the relevant address lines are high.

GadgetUK · Nov 6, 2013

This is what I am proposing:-

380000 = top 3 address lines (1110000000000000000000)
340000 = top 4 address lines (1101000000000000000000)
300000 = top 2 address lines (1100000000000000000000)

So, if I AND the top 4 address lines (and take into account that the 4th from top bit needs to be low) that go into C1, I can work out when address 380000h is selected, as per addressing C1 itself. I was worried I might need to AND all 16 address lines (possibly even 24??!?). Anyway, that part looks sound to me. If I then AND the output of that logic with the inverted input, into D10, whenever those address lines are high the D10 will reflect the P2 start button input.

But... I am assuming I need to use one of these (or another?) in order to work out that the CPU is requesting a read, so I dont inadvertantly output when its not reading - therefore not output on D10 at the wrong time.

UDS
LDS
AS

Does anyone know enough about the way the 68000 interacts with things like C1 in order to confirm which of those pins I need to take into my AND logic? I believe this could work. It won't be an elegant fix but the idea that I can use 1 or 2 AND chips and a NOT gate to fix this appeals to me right now.

GadgetUK · Nov 6, 2013

Looking at the 68000 user manual, I think I would need to AND output with the R/W pin and the address pins passed to the C1 chip. I've ordered some AND gates and a NOR for the bits that will need inverting (some address lines, and the output to D10). Will have ago, might have to get logic analyser out yet but it's pretty cheap (dangerous prototypes) so will avoid that until I get desperate.

GadgetUK · Nov 9, 2013

I haven't tried this yet as I think timing is going to be a big problem... The AND and NOR gates I was going to use have propagation time of ~6uS, but it dawned on me last night the CPU running at 12Mhz means typical operations would be x number of cycles in the nano second range. I've got no idea how many cycles it would take the CPU to assert 380000h address and then read bit D10, I don't know whether there's a delay to allow C1 time to output, or whether the CPU checks another pin out from C1 to indicate its ready. Too many unknown =\

For the moment I've focused on modifying the BIOS to feed P2 start through the service button. I've spoken to Razoola about this and he's told me what I suspected, that unlicensed games might not work - but I've got a mad idea to get around that, possibly write a value somewhere in memory using the memory editor in order to start the game that way (just for the odd game), but official games should work that way.

Will update as I make more progress. Any advice welcome. And if anyone has a neo-c1 for sale please let me know.

shadowkn55 · Nov 9, 2013

There is a fatal flaw in the logic decoding you proposed. You're missing the two leading zeros in high nibble of the address bus. 3'h = 0011, not 11. Lastly the one bit you're using to decode 8'h conflicts with A'h, the system registers. You're going to need 7 bits to properly decode 38'h and more than just AND and OR gates. Some hex inverters and data latches are required too. It's a lot of work just to get one button to function again. Replacing C1 or getting another board is probably easier.

mr aize · Nov 9, 2013

Maybe a silly question, but what bios are you using? I thought I had a similar problem with my 1 slot, when I changed the region using unibios. Suddenly I couldn't start player 2 any more. Turned out, one of the regions requires 2 separate coin slots, so every time I added coins, it just credited player 1, because my cab was only wired for 1 coin slot. Changed the region back and it worked fine.

GadgetUK · Nov 9, 2013

mr aize said:
Maybe a silly question, but what bios are you using? I thought I had a similar problem with my 1 slot, when I changed the region using unibios. Suddenly I couldn't start player 2 any more. Turned out, one of the regions requires 2 separate coin slots, so every time I added coins, it just credited player 1, because my cab was only wired for 1 coin slot. Changed the region back and it worked fine.

Thanks, it was worth posting but unfortunately its definitely a hardware fault with my neo-c1. I am using a unibios and i've taken the battery out just to ensure there's nothing dodgy in backup RAM affecting it - so i've ruled that out. Changed to all 3 regions and tried both arcade and aes.

GadgetUK · Nov 9, 2013

shadowkn55 said:
There is a fatal flaw in the logic decoding you proposed. You're missing the two leading zeros in high nibble of the address bus. 3'h = 0011, not 11. Lastly the one bit you're using to decode 8'h conflicts with A'h, the system registers. You're going to need 7 bits to properly decode 38'h and more than just AND and OR gates. Some hex inverters and data latches are required too. It's a lot of work just to get one button to function again. Replacing C1 or getting another board is probably easier.

Thanks, yes, I had already planned out using 7 address lines (the lines that feed into the neo-c1 chip), but not sure why you think I need a hex invertor or data latches? Just interested from an educational perspective really - I am not a guru, more of a novice (still learning here). I cannot see what's wrong with AND'ing the relevant address lines (some would need inverting via a NOR gate first), so when the address is say 0011100 (00380000h), and the R/W pin high I would feed the input into D10 directly, when the condition is not met with the AND logic I would feed the existing output of C1 chip into D1 as normal. The only problem I could see with that is one of timing - ie. it needs to all take place with x number of nano seconds in order to be able to happen quick enough in order that it works in the same way it would via the C1 chip as normal. Anyway, I think timing is the killer here. Ideally I would need to get a logic analyser onto the job to see what's happening at the moment regards timing.

Things like this really make you appreciate what the chips are doing... There's a lot of goodness packed in there lol.

shadowkn55 · Nov 10, 2013

It's not good practice to tie the outputs of a normal logic gate to a data bus. You'll get conflicts when other peripherals try to access the bus. The data latch, a transceiver actually, is used to tri-state the output to a high impedance level when the cpu doesn't need to read from the joysticks. You don't have to use a hex inverter to perform the decoding. It was a suggestion since there are infinite ways to do the same thing. Strictly using vanilla ANDs and ORs won't get you the desired result. You need an inverting gate of some sort in there to properly decode the address. You can decode anything with only NAND or NOR gates bu the wiring can get messy. Simplicity is key here so you'll want to find the solution with the least amount of ICs since it's already going to be at least 3+ parts.

GadgetUK · Nov 10, 2013

Ahha!!! Thank you, yes, I can see now, I did wonder why tri state IC's were used in lot of digital systems - that totally explains it. Thanks ever so much =) I've learnt so much recently thanks to people like you =)

Razoola · Nov 10, 2013

As per our email, this can also be done via ASM in the Bios. One patch would be needed to knock out the service button adding credits. Then a few lines of ASM and a call to it in the right place and its done, something like.

MOVE.B 0x380000,D1
AND.B #0xFB,D1 force bit 2 low on 0x380000 state (so value is always constant in this bit)
MOVE.B 0x320001,D2
AND.B #0x04,D2 clear out unneeded from 0x320001 state (keep bit 2 only)
ADD.B D2,D1 place bit2 from 0x320001 into state from 0x380000

Probably extra patching would be needed to fix the input test screen but I suspect its best to leave that alone.

GadgetUK · Nov 10, 2013

Thanks for the info =)

In more recent news... Today the MV-1FZ has decided to develop a Z80 communication fault - omg, the problems with this MVS never end...

One minute I was playing Top Golf with no problems. Left the room for 5 mins, came back and found no sound... Rebooted it 'Z80 communications error'. Taken it all appart, everything looks OK - nothing getting warm etc. WTF!!!

I've now got to go on a crusade to work out wtf is wrong with the Z80...

GadgetUK · Nov 30, 2013

Thanks to Xian Xi for the spares board!!! Fitted the neo-c1 and its all sorted!

Finally the MV-1FZ is working 100%, but now my 120 in 1 cart is acting strangely lol - others all fine. God I am jinxed lol... The cart is weird, I started getting artifacts on screen, reboot and got black ticking watchdog reset. Messed with the cart - resolder some ROM and CPLD pins and then it started working fine. 20 mins later same problem.

Now it starts but causes games (Top Hunter, NAM) to slow down with very slight artifacting - lines and the odd coloured block. I know it's cart related because same games are fine on other cart etc.

Xian Xi · Nov 30, 2013

GadgetUK said:
Thanks to Xian Xi for the spares board!!! Fitted the neo-c1 and its all sorted!

Finally the MV-1FZ is working 100%, but now my 120 in 1 cart is acting strangely lol - others all fine. God I am jinxed lol...

Multi carts are never dependable. I've had one that I owned for a year that just crapped out one day.

GadgetUK · Dec 1, 2013

Xian Xi said:
Multi carts are never dependable. I've had one that I owned for a year that just crapped out one day.

Yeah, they are very poor quality arent they =/ I wish they wouldnt use recycled chips - or at least test them or do some burn in testing or something. It seems like it's primarily an issue with the crappy reclaimed NVROM chips they use. I think the CPLD's are OK. There's very little on these boards to fail really, other than a little CPU.

Anyway, thanks again for the parts board!!!!

Video will be on YouTube in about 20 mins.

https://www.youtube.com/watch?v=8NYx3CTbpaw

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