This is what I am proposing:-
380000 = top 3 address lines (1110000000000000000000)
340000 = top 4 address lines (1101000000000000000000)
300000 = top 2 address lines (1100000000000000000000)
So, if I AND the top 4 address lines (and take into account that the 4th from top bit needs to be low) that go into C1, I can work out when address 380000h is selected, as per addressing C1 itself. I was worried I might need to AND all 16 address lines (possibly even 24??!?). Anyway, that part looks sound to me. If I then AND the output of that logic with the inverted input, into D10, whenever those address lines are high the D10 will reflect the P2 start button input.
But... I am assuming I need to use one of these (or another?) in order to work out that the CPU is requesting a read, so I dont inadvertantly output when its not reading - therefore not output on D10 at the wrong time.
UDS
LDS
AS
Does anyone know enough about the way the 68000 interacts with things like C1 in order to confirm which of those pins I need to take into my AND logic? I believe this could work. It won't be an elegant fix but the idea that I can use 1 or 2 AND chips and a NOT gate to fix this appeals to me right now.