MVS1AX & DTACK (again)

[tcdev]

Hi Guys,

A while back I posted a Q about a problem I had half-solved on my MVS1AX board. I found DTACK wasn't been driven so I pulled it active and now my board runs.

Nightmare Tony was kind enough to reply to my post but I guess I wasn't clear enough about what I was after?!?

I know what DTACK *is*, I just don't know how it's generated on the NeoGeo MB!?! I suspect it's a certain PAL, but w/o the schematics it's hard to tell!

So can anyone (Nightmare?) provide any more information about this problem? I'd like to be able to fix this problem properly once-and-for-all. With all the posts about dead MVS boards, I suspect that I'm not the 1st to see this problem?!?

Regards,
Mark

 

[Daisuke Jigen]

Question: why would an arcade board output a 50 hz signal?

 

[Nightmare Tony]

1. 50 Hz may be because of the country the unit was made; they may be using it as an interrupt or something.

2,. For the DTACK, I *THINK* it gets generated within the Neo-C0 on the older boards. It seems to be more tied in with the various addressing circuits. I do forget till If ind the schematics once again (the word dig comes to mind, I am also looking for 3 books but I dont think I will find them before the end of the year. They are one on the making of titanic, a book on civil engineering for aqmusement park ride design, and Imajica 2....

 

[JHendrix]

DTACK is used by the 68000 to signify that the data bus is ready to be read.

Setting it high would be a very bad thing to do since it would lead to reading the bus before it was stable to be read.

I have a single board computer I built for a lab using a 68000 varient and I could check what is driving DTACK, its a normal IC, you could try tracing the traces back to the pin its used on (assuming the Neo only has a 2 layer (top/bottom) circuit schematic.

 

[MKL]

Daisuke Jigen:
Question: why would an arcade board output a 50 hz signal?

WTF???

The PAL he's talking about is a type of IC, Programmable Array Logic...nothing to do with the European video standard (Phase Alternating Line).

 

[tcdev]

First of all, MKL is indeed correct, PAL has nothing to do with the video standard!!!

Nightmare Tony, thanks for the info, I'll check out the board again, but without the PAL equations, it won't be easy to work out the problem?!?

As for JHendrix, yes - I know the "fix" is a bad thing, but at the moment it's my only choice!

Unfortunately, your little computer won't tell me anything. The DTACK signal is used by peripherals to tell the 68K that the data is ready on the bus. Typically, components like ROM etc don't normally output such a signal, so external cctry must provide the DTACK for the 68k.

The NeoGeo would use a PAL to generate different timings based on the upper address lines, depending on what type of memory/port was being accessed, for example. So if the PAL is kaput, then replacing that is going to be a problem without the equations.

Hmmm... if anyone is familiar with the fpgaarcade project... it'd be fun to implement a NeoGeo in an FPGA!

Regards,
Mark