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Thread: Stuck C-ROM data lines on MV4 board?

  1. #1
    . avramce's Avatar
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    Stuck C-ROM data lines on MV4 board?

    Hi all, I have a MV4 board with a single working slot (slot 1) with the other 3 slots just giving a garbled output at the moment. The audio and gameplay on Slot 1 is fine, however, I have lines going through the sprite layer, which I believe implies a stuck C-ROM data line if I am understanding the neogeodev wiki: https://wiki.neogeodev.org/index.php...hes#C_ROM_data

    Screen Shot 2019-10-23 at 9.49.31 AM.pngScreen Shot 2019-10-23 at 9.49.18 AM.png

    I've been reading the wiki regarding the C-ROM addresses and data flow from the LSPC-A0 to the cart, then cart to the NEO-273 (for Bust-A-Move), but I'm stumped on where to continue from there. I was looking at the MVS cart pin out and trying to make sense of the meanings of CR0 through CR31, but cannot seem to map my understanding on how those pins associate with the C-ROM data.

  2. #2
    . avramce's Avatar
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    Read into it a bit more, so CR0 through CR 31 are the C-ROM data into the board, right? Does that mean that I should check the PRO-CTO to see if any of those pins stay high or low during gameplay?:
    https://wiki.neogeodev.org/index.php?title=PRO-CT0

    I assume that it will be easier to read that off the cart slot rather than the CTO since it is on the secondary board. Is there any difference with reading the line with an oscilloscope vs a data probe?

  3. #3
    Geese's Thug
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    First thing I would do it make sure your slot is clean.

    The CR pins on the slots are input pins on all those F253 chips on the outer edge of the slot board. The F253s are 4:1 multiplexers (2 sets), so for example the CR0 pin from each slot will go into the same F253, the F253 will pick the correct CR0 input (based on which slot is suppose to be active) and forward it along to the output pin, which gets sent to the cpu board via one of those large interconnect between the boards.

    I dont have the mapping for slot 1 cha board, but I do have it for slot 2. All the CR pins from a slot should land on the same 2 pins on the F253s. It looks like for slot 2 that's pin 5 and 11. You will need to figure out what those 2 pins are for slot 1 and adjust the following info accordingly. Then I would suggest doing logic probe tests on the F253s to make sure you are seeing signal for the slot 1 inputs and that the output mimic what you get on the input.

    Code:
    SLOT 2:
    CHA (CTRG3)
     01A <=> GND
     02A <=> GND
     03A <=> PIN 12 on LS244 @ E4
     04A <=> PIN 14 on LS244 @ E4
     05A <=> PIN 16 on LS244 @ E4
     06A <=> PIN 18 on LS244 @ E4
     07A <=> PIN 09 on LS244 @ E4
     08A <=> PIN 07 on LS244 @ E4
     09A <=> PIN 05 on LS244 @ E4
     10A <=> PIN 03 on LS244 @ E4
     11A <=> PIN 12 on LS244 @ E3
     12A <=> PIN 14 on LS244 @ E3
     13A <=> PIN 16 on LS244 @ E3
     14A <=> PIN 18 on LS244 @ E3
     15A <=> PIN 09 on LS244 @ E3
     16A <=> PIN 07 on LS244 @ E3
     17A <=> PIN 05 on LS244 @ E3
     18A <=> PIN 03 on LS244 @ E3
     19A <=> PIN 05 on  F253 @ B1
     20A <=> PIN 05 on  F253 @ C1
     21A <=> PIN 05 on  F253 @ D1
     22A <=> PIN 05 on  F253 @ E1
     23A <=> PIN 05 on  F253 @ F1
     24A <=> PIN 05 on  F253 @ G1
     25A <=> PIN 05 on  F253 @ N1
     26A <=> PIN 05 on  F253 @ P1
     27A <=> PIN 05 on  F253 @ R1
     28A <=> PIN 05 on  F253 @ S1
     29A <=> VCC
     30A <=> VCC
     31A <=> VCC
     32A <=> VCC
     33A <=> PIN 05 on  F253 @ A7
     34A <=> PIN 05 on  F253 @ B7
     35A <=> PIN 05 on  F253 @ C7
     36A <=> PIN 05 on  F253 @ H7
     37A <=> PIN 05 on  F253 @ J7
     38A <=> PIN 05 on  F253 @ K7
     39A <=> NC
     40A <=> NC
     41A <=> NC
     42A <=> PIN 19 on LS245 @ G3/G4/H5/H6/F5 (also connects to 42A on PROG slot2)
     43A <=> PIN 12 on LS244 @ E6
     44A <=> PIN 14 on LS244 @ E6
     45A <=> PIN 16 on LS244 @ E6
     46A <=> PIN 18 on LS244 @ E6
     47A <=> PIN 09 on LS244 @ E6
     48A <=> PIN 07 on LS244 @ E6
     49A <=> PIN 05 on LS244 @ E6
     50A <=> PIN 03 on LS244 @ E6
     51A <=> PIN 12 on LS244 @ E5
     52A <=> PIN 14 on LS244 @ E5
     53A <=> PIN 16 on LS244 @ E5
     54A <=> PIN 18 on LS244 @ E5
     55A <=> PIN 09 on LS244 @ E5
     56A <=> PIN 07 on LS244 @ E5
     57A <=> PIN 05 on LS244 @ E5
     58A <=> PIN 03 on LS244 @ E5
     59A <=> GND
     60A <=> GND
    
     01B <=> GND
     02B <=> GND
     03B <=> PIN 12 on LS244 @ F4
     04B <=> PIN 14 on LS244 @ F4
     05B <=> PIN 16 on LS244 @ F4
     06B <=> PIN 18 on LS244 @ F4
     07B <=> PIN 03 on LS244 @ F4
     08B <=> PIN 05 on LS244 @ F4
     09B <=> PIN 07 on LS244 @ F4
     10B <=> PIN 09 on LS244 @ F4
     11B <=> PIN 12 on LS244 @ F2
     12B <=> PIN 14 on LS244 @ F2
     13B <=> PIN 16 on LS244 @ F2
     14B <=> PIN 18 on LS244 @ F2
     15B <=> PIN 03 on LS244 @ F2
     16B <=> PIN 05 on LS244 @ F2
     17B <=> PIN 07 on LS244 @ F2
     18B <=> PIN 09 on LS244 @ F2
     19B <=> PIN 11 on  F253 @ B1
     20B <=> PIN 11 on  F253 @ C1
     21B <=> PIN 11 on  F253 @ D1
     22B <=> PIN 11 on  F253 @ E1
     23B <=> PIN 11 on  F253 @ F1
     24B <=> PIN 11 on  F253 @ G1
     25B <=> PIN 11 on  F253 @ N1
     26B <=> PIN 11 on  F253 @ P1
     27B <=> PIN 11 on  F253 @ R1
     28B <=> PIN 11 on  F253 @ S1
     29B <=> VCC
     30B <=> VCC
     31B <=> VCC
     32B <=> VCC
     33B <=> PIN 11 on  F253 @ A7
     34B <=> PIN 11 on  F253 @ B7
     35B <=> PIN 11 on  F253 @ C7
     36B <=> PIN 11 on  F253 @ H7
     37B <=> PIN 11 on  F253 @ J7
     38B <=> PIN 11 on  F253 @ K7
     39B <=> PIN 05 on  F253 @ L7
     40B <=> PIN 11 on  F253 @ L7
     41B <=> PIN 05 on  F253 @ M7
     42B <=> PIN 11 on  F253 @ M7
     43B <=> PIN 05 on  F253 @ N7
     44B <=> PIN 11 on  F253 @ N7
     45B <=> PIN 05 on  F253 @ P7
     46B <=> PIN 11 on  F253 @ P7
     47B <=> PIN 12 on  F244 @ F6
     48B <=> PIN 14 on  F244 @ F6
     49B <=> PIN 16 on  F244 @ F6
     50B <=> PIN 18 on  F244 @ F6
     51B <=> PIN 11 on LS245 @ F5
     52B <=> PIN 12 on LS245 @ F5
     53B <=> PIN 13 on LS245 @ F5
     54B <=> PIN 14 on LS245 @ F5
     55B <=> PIN 15 on LS245 @ F5
     56B <=> PIN 16 on LS245 @ F5
     57B <=> PIN 17 on LS245 @ F5
     58B <=> PIN 18 on LS245 @ F5
     59B <=> GND
     60B <=> GND

  4. #4
    . avramce's Avatar
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    Thanks Ack, that helps tremendously. If I go through the debugging for the cart slots, would you want me to contribute and create a mapping table for slots 1, 3 and 4?

  5. #5
    Geese's Thug
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    Quote Originally Posted by avramce View Post
    Thanks Ack, that helps tremendously. If I go through the debugging for the cart slots, would you want me to contribute and create a mapping table for slots 1, 3 and 4?
    I have a full mapping for slot 4, and usually just use that to figure out the other slots as I need them.

  6. #6
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    Necro'ing this old thread. I couldn't find anything wrong with the top board, and eventually got my hands on a board with all 4 slots working. Testing it on the board mentioned on this thread, all four slots at displaying the same gfx issue. Leads me to believe that there is a bad trace on the lower board, but what chip should I be looking at? Once the CROM data is sent from the carts, what receives it on the lower board? Is that the PRO_CT0? Or is the CROM data returned to the LS-PCA0?

    Re-reading this page (https://wiki.neogeodev.org/index.php...#C_ROM_address), but the debugging/data flow chart stops after the CROM data is fetched from the cart.

  7. #7
    Geese's Thug
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    C ROM data should go from the output pins of the F253s on the top board to the PRO-CT0 chip on the lower board. The LSPC-A0 should be what is setting the address lines on the C ROMs.

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