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Thread: Neo Diagnostics ROMs

  1. #101
    Vice's Love Slave
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    c1 - signal - 68k
    20 - a17 - 45
    21 - a18 - 46
    22 - a19 - 47
    23 - a20 - 48
    24 - a21 - 49
    25 - a22i - 55 on neo-e0
    26 - a23i - 56 on neo-e0
    32 - rw - 9
    33 - uds - 7
    34 - lds - 8
    35 - as - 6
    36 - clk - 15

  2. #102
    JammaNationX
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    Quote Originally Posted by shadowkn55 View Post
    c1 - signal - 68k
    20 - a17 - 45
    21 - a18 - 46
    22 - a19 - 47
    23 - a20 - 48
    24 - a21 - 49
    25 - a22i - 55 on neo-e0
    26 - a23i - 56 on neo-e0
    32 - rw - 9
    33 - uds - 7
    34 - lds - 8
    35 - as - 6
    36 - clk - 15
    Thanks, I'll check them now.

  3. #103

  4. #104
    Vice's Love Slave
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    Quote Originally Posted by Xian Xi View Post
    All 100% except A21 as it's tied to +5v on AES.
    That doesn't sound right. The system uses A21 to toggle between p-rom/wram and the memory mapped registers.

  5. #105
    JammaNationX
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    Quote Originally Posted by shadowkn55 View Post
    That doesn't sound right. The system uses A21 to toggle between p-rom/wram and the memory mapped registers.
    Pin 49 from the 68k goes directly to a bypass cap right above the 68k and nowhere else. I'll double check.

  6. #106
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    Made on a mistake on the location of a21 on the 68k. It's pin 50. Pin 49 is vcc.

  7. #107
    JammaNationX
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    Quote Originally Posted by shadowkn55 View Post
    Made on a mistake on the location of a21 on the 68k. It's pin 50. Pin 49 is vcc.
    That pin is fine as well.

  8. #108
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    Quote Originally Posted by Xian Xi View Post
    Same System as above.

    If I run the d-bios with a cart installed it is able to display on the screen.

    I get:

    WRAM Address (A8-A14)
    Address: 100400
    Actual: 4202
    Expected: 0202
    WRAM Test Only (AES)

    Reset and tried again:

    WRAM Address (A8-A14)
    Address: 100000
    Actual: 4040
    Expected: 0000
    WRAM Test Only (AES)
    You always need a cart inserted to get any text on screen with AES but it doesn't matter which game. It will look like it hasn't booted if you don't have a cart inserted.

    Do you keep getting similar address errors like the ones in that quote? Both WRAM A9 pins run straight to the 68k. Are those connected? The A8~A14 is the range it reported but I think A9 has problems from those codes.
    Last edited by smkdan; 09-13-2013 at 10:47 AM.

  9. #109
    JammaNationX
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    Quote Originally Posted by smkdan View Post
    You always need a cart inserted to get any text on screen with AES but it doesn't matter which game. It will look like it hasn't booted if you don't have a cart inserted.

    Do you keep getting similar address errors like the ones in that quote? Both WRAM A9 pins run straight to the 68k. Are those connected? The A8~A14 is the range it reported but I think A9 has problems from those codes.
    Yes, the codes are always similar. The upper address lines have 100% continuity. Is it looking like a bad 68k?

  10. #110

  11. #111
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    Quote Originally Posted by Xian Xi View Post
    I can confirm that with MV1 boards when using the d-bios, it just shows a black screen.
    Any text showing up before the black screen? Do you remember always getting this with MV1 boards and do you have any other 1st gen chipset boards (MV2/4/6) to check with? I test it on all the AES/MVS boards I have before releasing but I don't have any old enough to use the 1st gen chipset. There shouldn't be any major difference that causes something like this but I don't have a way to rule it out myself. I'll do another trial run on my 1 slots when I have the time (MV1F/T) but I remember it working fine in all cases there.

  12. #112
    JammaNationX
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    Quote Originally Posted by smkdan View Post
    Any text showing up before the black screen? Do you remember always getting this with MV1 boards and do you have any other 1st gen chipset boards (MV2/4/6) to check with? I test it on all the AES/MVS boards I have before releasing but I don't have any old enough to use the 1st gen chipset. There shouldn't be any major difference that causes something like this but I don't have a way to rule it out myself. I'll do another trial run on my 1 slots when I have the time (MV1F/T) but I remember it working fine in all cases there.
    It must be the first gen chipset since it did that as well with the 1st gen AES I tried it on. On MVS 1st gen chipset, it's as if it loses sync. It will show the normal text for a split second then the picture bends into blackness. On some 1st gen boards it will keep resetting when it gets to the WRAM/BRAM test but if I press A+B+C+D I can't test the WRAM/BRAM normally.

  13. #113
    JammaNationX
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    3-6 AES System:

    Pallette Bank0 Data (0000)
    Address: 400978
    Actual: F3FB
    Expected: 0000
    Passes: 0000000

    Pallette Address (A0-A7)
    Address: 400000
    Actual: 1010
    Expected: 0000
    Passes: 0000000

  14. #114
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    Quote Originally Posted by Xian Xi View Post
    3-6 AES System:

    Pallette Bank0 Data (0000)
    Address: 400978
    Actual: F3FB
    Expected: 0000
    Passes: 0000000

    Pallette Address (A0-A7)
    Address: 400000
    Actual: 1010
    Expected: 0000
    Passes: 0000000
    How do the control pins look to/from NEO-G0 and palette RAM? (PAL,R/W,PALWE). G0 substitutes the 2x 74245 and 1x 7432 on MVS boards if that's any help. Palette RAM /OE should be grounded on both too. Anything else noticable that could be related?

    http://wiki.neogeodev.org/index.php?...-G0#AES_pinout

    About the 1st gen stuff where the screen blacks out, does it make any difference if you have a cart inserted even without doing the sound tests?

  15. #115
    JammaNationX
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    NEO-G0 has 100% continuity.

    I used this pinout:

    Code:
    NEO-AES3-6 COLOR RAM
    
    F1
    
    1	VCC
    2	HC259 (12)
    3	NEO-B1 (12)
    4	NEO-B1 (11)
    5	NEO-B1 (9)
    6	NEO-B1 (8)
    7	NEO-B1 (3)
    8	NEO-B1 (2)
    9	NEO-B1 (159)
    10	NEO-B1 (158)
    11	LS273 (8) H1, NEO-G0 (35)
    12	LS273 (13) H1, NEO-G0 (36)
    13	LS273 (14) H1, NEO-G0 (37)
    14	GND
    15	LS273 (17) H1, NEO-G0 (38)
    16	LS273 (3) H2, NEO-G0 (53)
    17	LS273 (14) H2, NEO-G0 (54)
    18	LS273 (7) H1, NEO-G0 (55)
    19	LS273 (18) H1, NEO-G0 (56)
    20	GND
    21	NEO-B1 (31)
    22	GND
    23	NEO-B1 (32)
    24	NEO-B1 (29)
    25	NEO-B1 (28)
    26	VCC
    27	NEO-G0 (41)
    28	VCC
    
    G1
    
    1	VCC
    2	HC259 (12)
    3	NEO-B1 (12)
    4	NEO-B1 (11)
    5	NEO-B1 (9)
    6	NEO-B1 (8)
    7	NEO-B1 (3)
    8	NEO-B1 (2)
    9	NEO-B1 (159)
    10	NEO-B1 (158)
    11	LS273 (4) H2, NEO-G0 (62)
    12	LS273 (7) H2, NEO-G0 (63)
    13	LS273 (8) H2, NEO-G0 (64)
    14	GND
    15	LS273 (13) H2, NEO-G0 (1)
    16	LS273 (17) H2, NEO-G0 (21)
    17	LS273 (18) H2, NEO-G0 (22)
    18	LS273 (3) H1, NEO-G0 (23)
    19	LS273 (4) H1, NEO-G0 (24)
    20	GND
    21	NEO-B1 (31)
    22	GND
    23	NEO-B1 (32)
    24	NEO-B1 (29)
    25	NEO-B1 (28)
    26	VCC
    27	NEO-G0 (41)
    28	VCC

  16. #116

  17. #117
    JammaNationX
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    I also have an FZS board, the graphics are messed up but running the D-bios and it passes all tests so would the 273s cause this on the output before the DAC? The glitches look like text on the screen as if it's the fix layer that's a problem.

  18. #118
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    Quote Originally Posted by Xian Xi View Post
    Pulled the palette RAM and it tested good. I hope it isn't a bad NEO-B1.
    If you know continuity is all good (and it probably is if it manages to reach the address test) then it may be the G0 itself or the B1. If B1 doesn't reliably pass through the address to palette RAM or if the G0 enable circuit isn't good then these intermittent errors would make sense. There's not much else to palette RAM access on later AES. There's the NEO-C1 too but it only has the single "PAL" pin you checked already so I think it's a slim chance of it being bad.

    Got a photo of these glitches and does it look anything in the wiki glitches article? I'd only blame the DAC if all the graphics look glitch free pixel perfect but the RGB output was unbalanced, lacking intensity or having color banding on certain channels etc.
    Last edited by smkdan; 10-05-2013 at 05:28 AM.

  19. #119

  20. #120
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    It does look FIX related. Does the board get far enough into the test menu or game title screen (something recognizable) for you to take a pic of it? My guess from that error is FIX address but it's hard to tell since I don't know what that text is meant to say.

  21. #121
    JammaNationX
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    Quote Originally Posted by smkdan View Post
    It does look FIX related. Does the board get far enough into the test menu or game title screen (something recognizable) for you to take a pic of it? My guess from that error is FIX address but it's hard to tell since I don't know what that text is meant to say.
    If I bring up the menu you can kinda see the menu but it looks kinda scrambled. I'll snap a pic.

  22. #122
    JammaNationX
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    Now the board is in watchdog mode. When I probe everything from 3-19(except 11) I get a logic high pulse while everything from 21-37 pulses low/high.

  23. #123
    JammaNationX
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    Quote Originally Posted by smkdan View Post
    It does look FIX related. Does the board get far enough into the test menu or game title screen (something recognizable) for you to take a pic of it? My guess from that error is FIX address but it's hard to tell since I don't know what that text is meant to say.
    In the picture above is the test menu so I'm guessing it's the calendar text.

  24. #124
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    Did you get anywhere after it randomly started resetting?

    I'm going to start looking for a reasonably priced 1st gen chipset board so I can figure out why the BIOS behaves strangely on them. I have a few guesses but no good way to confirm them.

  25. #125
    Hades Gate Keeper
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    If possible, please make the NDR work with larger eproms.

    Would like to stack the image and put it on a larger rom and toss that on the neo.

    Last time I tried: No go. Black screen.

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