pranslation and !arcade! converter uses original SNK ASICs taken from mvs carts to give the home system hardware the correct set of signals it is expecting. When SNK started to include encryption, these ASICs where drastically changed to support it thus these converters don´t play encrypted games.
The ASICs were expanded for bankswitching and encryption but the tile serialization is exactly the same.
Super neo converter 1 & 2 are FPGA implementations of SNK ASICs, the programmer was able to overcome the issue that keeping encrypted games from working but his implementation is not perfect hence the scaling issues and other small problems, a simple firmware upgrade of the FPGA could have all those small problems ironed out but the unit has no service connector for it.
Does a SMVSC1 even exist? I don't think so. Anyways, they don't contain a FPGA, but a mask ASIC by NeoFlash (at least it's badged that way). In the prototype they used an Altera CPLD. The PROG board also has a PAL and buffers used to gate the data bus presumably to thwart copy protection, I haven't bothered to factor the logic. The CHA conversion logic does nothing but serialize the tiles, it's not necessary to do anything for encrypted games.
The actual necessary logic for a converter is pretty small, 15x 74 series chips, or a 32+ flip flop PLD with sufficient I/O.
BTW, I think any difference in compatibility between revisions (and possibly the scaling) would have to be because of changes in the fetch state machine. The serialization logic is kinda strange (it goes way back to early arcade games) so it's understandable they took a little liberty with the implementation and didn't carry out exhaustive tests.
It's hard to tell what the artifacts in the photos/video are from. It could be that bitplanes are fetched in a different order for scaled tiles or the converter can't flip the tile mid shifting bits out. I'm confident though that my logic will work exactly like the real thing, I just have to hack up a converter :\ If only the SMVSC2 did contain a FPGA I'd JTAG it immediately.
